A primary way in which modern microprocessors reduce their power consumption is to reduce the frequency and/or the voltage at which the microprocessor is operating. There are times when peak performance is required of the microprocessor such that it needs to be operating at its highest voltage and frequency. Other times, operating at more power-efficient voltages and frequencies is adequate. Accordingly, many modern microprocessors are capable of operating at many different voltages and/or frequencies. The well-known Advanced Configuration Power Interface (ACPI) Specification facilitates operating system-directed power management by defining power performance states, known as “P-states,” that represent different voltage and frequencies for operating a microprocessor.
Performing power management actions is complicated by the fact that many modern microprocessors are multi-core processors in which multiple processing cores share one or more power management-related resources. For example, the cores may share voltage sources and/or clock sources. Furthermore, computing systems that include a multi-core processor also typically include a chipset that includes bus bridges for bridging the processor bus to other buses of the system, such as to peripheral I/O buses, and includes a memory controller for interfacing the multi-core processor to a system memory. The chipset may be intimately involved in the various power management actions and may require coordination between itself and the multi-core processor.
In early designs, the chipset was used to orchestrate power and thermal control. More recently, an article by Alon Naveh et al. entitled “Power and Thermal Management in the Intel Core Duo Processor” which appeared in the May 15, 2006 issue of the Intel Technology Journal, disclosed a power and thermal management architecture that uses an off-core hardware coordination logic (HCL), located in a shared region of the die or platform, that serves as a layer between the individual cores and shared resources on the die and platform. The HCL controls implementation of both ACPI C-states and P-states. More specifically, the HCL tracks P-state requests from both cores and calculates a CPU level target operating point that is either the higher or the lower performing of the two P-state requests, depending on whether the CPU is in a thermal control state.
In the scheme disclosed above, the HCL is centralized non-core logic outside the cores themselves that performs power management, including performance power state management, on behalf of all the cores. This centralized non-core logic solution may be disadvantageous, especially if the HCL is required to reside on the same die as the cores in that it may be yield-prohibitive due to large die sizes, particularly in configurations in which it would be desirable to include many cores on the die.